The present invention relates to a computer system having an address translation buffer and, more particularly, to the control system of a translation lookaside buffer.
In general, a computer system utilizing a virtual memory control system includes a translation lookaside buffer (to hereinafter referred to as a TLB). The TLB is used for the high-speed translating of a virtual address into a physical address (a real address), and stores a pair of virtual and physical addresses (address translation data) in each entry. In general, part of the virtual address is separated and used as an address (a TLB address) for referring to the TLB. Methods of separating part of the virtual address, i.e., the method of referring to the TLB can be categorized into two systems. A first system will now be described, with reference to FIG. 1.
In FIG. 1, TLB 11 having 2.sup.m+n entries. A virtual address to be translated into a physical address is stored in address register 12. The content of (m+n)-bit field 13 is loaded in TLB address register 14. The content of TLB address register 14 is used for designating entries in TLB 11.
FIG. 2 shows a state wherein TLB 11 in FIG. 1 is utilized. In virtual memory (address) space VS, each of virtual memory areas A.sub.p0 to A.sub.pi (i is determined by the size of virtual memory space VS) corresponds to the entire area of TLB 11. Therefore, the first system is efficient when a large continuous memory area is accessed, e.g., when a single program is to be executed. However, when areas to be accessed are distributed in areas A.sub.p0 to A.sub.pi, as indicated by hatched portions in FIG. 2, a TLB hit rate is decreased. As a result, the frequency of occurrence of replace operation is increased, resulting in poor efficiency. Such a state occurs, for example, when a program is executed in which code portions or data portions are distributed in a plurality of areas in virtual memory space VS, or when a plurality of programs are parallelly executed.
A second system will be described with reference to FIG. 3. In FIG. 3, TLB 21 having entry blocks T.sub.q0, T.sub.ql, . . . T.sub.qi (i=2.sup.m -1) constituted by 2.sup.n entries is used. A virtual address to be translated is stored in virtual address register 22. The contents of m-bit field 23 and n-bit field 24, which is discontinuous with field 23, in virtual address register 22 are linked together and loaded in TLB address register 25. TLB 21 is accessed by the content of TLB address register 25, and hence an entry in TLB 21 is designated. The second system is disclosed, e.g., in FIG. 1 of U.S. application Ser. No. 749,866, filed (patented) on June 28, 1985.
FIG. 4 shows a state wherein TLB 21 in FIG. 3 is utilized. Areas A.sub.q0 to A.sub.qi obtained by dividing virtual memory space VS by i+1 (i=2.sup.m -1) correspond to entry blocks T.sub.q0 to T.sub.qi in TLB 21, respectively. More specifically, for example, each area of 2.sup.n pages obtained by dividing area A.sub.q0 by j (j is determined by the size of A.sub.q0) corresponds to entryblock T.sub.q0 Therefore, the second system is very efficient when a program in which discontinuous areas in virtual memory space VS are accessed is to be executed, or when a plurality of programs are parallelly executed. However, the second system is very inefficient when a large continuous memory area in the virtual memory space is required. For example, when the entire area A.sub.q0 in virtual memory space VS shown in FIG. 4 is to be accessed, only entry block T.sub.q0 of TLB 21 is used, resulting in poor efficiency.
As described above, the conventional system capable of efficiently accessing a large continuous area in the virtual memory space is inefficient when a plurality of discontinuous areas in the virtual memory space are to be accessed, and the conventional system capable of efficiently accessing a plurality of discontinuous areas in the virtual memory space is inefficient when a large continuous area in the virtual memory space is to be accessed.